Design of built-in self-test using coding

Built-in Self-test of a digital circuit is carried out by using on-chip pattern generator to apply input vectors to the circuit under test (CUT). The output of the circuit is usually compressed using a signature analyzer. At the end of test application, the compressed signature is compared against the good circuit signature--a mismatch indicates that the CUT is faulty. However, due to the compression, even in the presence of some faults in the circuit, the circuit might be declared fault free. This is called aliasing. This report presents a coding theory based technique for computing the probability of aliasing. First, a general framework for shift register-based signature analysis is presented, and a mathematical model for this framework--based on coding theory--is developed. There are two key features of this formulation. Firstly, it allows for uniform treatment of LFSR, MISR and multiple MISR-based signature analyzers. In addition, using this formulation, a new compression scheme for multiple output CUT is proposed. Also developed are error models that take into account the circuit topology and the effect of faults at the outputs. A general error model is developed which subsumes all the commonly used error models. The coding theory framework is used to compute the exact value of aliasing probability. Several new results on aliasing are presented and certain known results are shown to be direct consequences of this formulation. An interesting method for self-test, in which concurrent checking and BIST are used simultaneously, is then presented. It is shown that the probability of aliasing for this method is negligible. Another advantage of the scheme is that the redundancy added to the CUT is useful during normal circuit operation as well