Area and time co-optimization for system-on-a-chip based on consecutive testability

Test access mechanism and test scheduling are integral parts of SoC test. This paper presents an area overhead and test time co-optimization method for SoCs based on consecutive testability. The proposed method creates TAM and a test schedule by using integer linear programming, and augments a given SoC into consecutively testable one where area overhead and test time are co-optimized. Consecutive testability of SoCs guarantees that arbitrary test/response sequences including timing information can be propagated to/from all embedded cores and all interconnects without information loss. Therefore, the method can handle any test sequence that requires consecutive application of test patterns at speed of system clock such as a test sequence for timing faults. Moreover, the proposed method achieves low area overhead because existing interconnects are used as a part of TAM. Experimental results show advantages of the proposed method compared to test bus architecture which is a well known TAM architecture.http://library.naist.jp/mylimedio/dllimedio/show.cgi?bookid=100049901&oldid=9217