Software-based delay fault testing of processor cores

Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in functional mode using its instruction set. This paper presents a software-based self-testing methodology for delay fault testing. Delay faults will affect the circuit functionality only when it can be activated in functional mode. A systematic approach for the generation of test vectors, which are applicable in functional mode, is presented. A graph theoretic model (represented by IE-Graph) is developed in order to model the datapath. A finite state machine model is used for the controller. These models are used for constraint extraction under which a test can be applied in functional mode. This approach uses instruction set architecture, RT level description along with gate level netlist for test generation.http://library.naist.jp/mylimedio/dllimedio/show.cgi?bookid=100037130&oldid=6791