Hardware architecture for a bidirectional hetero-associative Protein Processing Associative Memory

This paper details an extension to an architecture for robust bidirectional hetero-associative recall. Our proposed Protein Processor Associative Memory (PPAM) is fundamentally different from the traditional processing methods which use arithmetic operations and consequently Arithmetic and Logic Units (ALUs). In this paper, we improve on our initial work addressing concerns surrounding hardware implementation. We present the improved computational architecture, coupled with a corresponding hardware architecture for implementation. Results of applying the hardware implementation on a small dataset are included, along with reports from synthesis tools about hardware utilisation.