Add to ORKGThe program CELLINEX presented in the paper finds the cellular interconnections from the layout of cell-structured integrated circuits. From this the logical description of the circuit is generated and it is checked whether the realized interconnections are permitted or not and whether there are trivial lacks or not. The paper describes the characteristics of the program and the most important algorithms. Some kinds of documentation of the results are presented
We describe the use of a form of machine learning which makes efficient use of time and computing re...
Plagiarism of integrated-circuit (IC) layout is a problem encountered both in academia and in indust...
Methods are presented by which wiring data of an NMOS integrated circuit may be extracted from its m...
The program CELLINEX presented in the paper finds the cellular interconnections from the layout of...
Design verification is an essential step in the production of a custom integrated circuit because of...
This thesis presents the development of a layout automator for VLSI circuit design using a standard ...
This paper describes an IC layout methodology based on arbitrary outline cells, prevention of overla...
The steady down scaling of CMOS device dimensions has been the main stimulus to the growth of microe...
A new automatic IC mask layout code is described which avoids most of the problems inherent in the p...
The logic scaling following Moores law has reached a level where System on Chips (SoCs) commonly con...
A new algorithm and a software application for an automated system of input data preparation for int...
141 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1986.One method in solving the VLS...
In modern VLSI design it is of vital importance to know the influence of parasitics on the behaviour...
Thesis (Ph. D.)--University of Rochester. Dept. of Computer Science, 1984. Simultaneously published ...
[[abstract]]An automatic layout generation system, called LiB, for the small-scale integrated (SSI) ...
We describe the use of a form of machine learning which makes efficient use of time and computing re...
Plagiarism of integrated-circuit (IC) layout is a problem encountered both in academia and in indust...
Methods are presented by which wiring data of an NMOS integrated circuit may be extracted from its m...
The program CELLINEX presented in the paper finds the cellular interconnections from the layout of...
Design verification is an essential step in the production of a custom integrated circuit because of...
This thesis presents the development of a layout automator for VLSI circuit design using a standard ...
This paper describes an IC layout methodology based on arbitrary outline cells, prevention of overla...
The steady down scaling of CMOS device dimensions has been the main stimulus to the growth of microe...
A new automatic IC mask layout code is described which avoids most of the problems inherent in the p...
The logic scaling following Moores law has reached a level where System on Chips (SoCs) commonly con...
A new algorithm and a software application for an automated system of input data preparation for int...
141 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1986.One method in solving the VLS...
In modern VLSI design it is of vital importance to know the influence of parasitics on the behaviour...
Thesis (Ph. D.)--University of Rochester. Dept. of Computer Science, 1984. Simultaneously published ...
[[abstract]]An automatic layout generation system, called LiB, for the small-scale integrated (SSI) ...
We describe the use of a form of machine learning which makes efficient use of time and computing re...
Plagiarism of integrated-circuit (IC) layout is a problem encountered both in academia and in indust...
Methods are presented by which wiring data of an NMOS integrated circuit may be extracted from its m...