Improving Clock Synchronization Performance in Industrial Networks

The recent advances in cyber-physical systems and industrial internet-of-things (IIoT) have enabled the convergence of information technology (IT) and operational technology (OT) worlds of industrial automation systems achieving higher productivity, reliability, and revenues. The availability of business-critical and production-critical data on the converged network has enabled new and advanced network-centric applications that require time-constrained embedded devices to be connected to “the internet.'' The massively interconnected IIoT devices communicating in real-time require a accurate, scalable, easy-to-deploy, and cost-effective clock synchronization service for the ordering of information collected throughout a network. Thus, a time or clock synchronization service that aligns the devices' clocks in the network to ensure accurate timestamping and orderly event executions, has gained great importance. The industrial networks are heterogeneous in nature, where various grades of hardware resources along with varied software complexities operate in average to extremely harsh and hostile environments. The heterogeneity and the huge number of devices make it challenging to achieve an adequate level of clock synchronization in industrial networks with existing hardware and software-based solutions. For this reason, the thesis aims to enhance the accuracy of the most-economical, highly scalable, and easy-to-deploy software-based clock synchronization in wired industrial networks with the hypothesis that predictive software strategies can compensate for their lack of accuracy. The first step towards this goal is to identify the industrial network characteristics essential for improving clock synchronization. The analysis of real network data from an industrial site confirmed that packet delay variation (PDV) could assure the clock synchronization performance in an industrial network. Using signal processing-based PDV compensation methods, we propose enhanced clock synchronization algorithms, namely, 'CoSiNeT' and 'CoSiWiNet' for local and wide area industrial networks. Based on the analysis in real networks, both algorithms outperform state-of-the-practice and state-of-the-art methods in degrading network scenarios. Once the significance of PDV in synchronization performance has been confirmed, the next step is identifying the network parameters significantly affecting PDV. The thesis provides a network calculus-based PDV analysis of synchronization messages in a multi-stage wired packet-switched network under the presence of stochastic background traffic. The analysis, based on a closed-form, end-to-end probabilistic analytical model of PDV, identifies the network parameters that significantly affect PDV. It further unveils the significant relationship between PDV incurred by synchronization messages and the rate, burstiness of background network traffic parameters. Bounding the PDV or jitter under a certain level can be beneficial for applications such as synchronization, where PDV is a significant decider of assured performance. A Sigma traffic shaper is proposed to maintain PDV under limits by controlling the rate of incoming background traffic at the ingress port of the network. We further estimate the probability of a synchronization message loss due to the shaper, given the finite buffers available at network stages. The loss probability estimation is a vital trade-off tool that can be utilized to fix the limiting rate for a desired PDV maintenance. Finally, we extend the PDV analysis to predict the probabilistic clock synchronization accuracy bound for given network conditions. The performance analysis conducted with proposed configurations showed that limiting the arrival traffic rate to 50% resulted in PDV levels and in turn synchronization accuracy being reduced from a few milliseconds to a few microseconds