Design of an acquisition card mixed signals analog/digital based on FPGA for CERN’s Beam Energy Tracking Systems

This project handles the design of the acquisition card of CERN's Beam Energy Tracking System (BETS). It is used for multiple purposes but mainly for the Large Hadron Collider Beam Dumping System (LBDS) and the Super Proton Synchrotron Beam Dumping System (SBDS). In this work a new hardware and hardware description language (named gateware) design is done for the Beam Energy Acquisition (BEA) card. First, the state of the technology is done by describing the current system from 2004 as well as the new LBDS-BETS specification. Second, the electronic development is realized. It starts with the hardware architectures, the choice of the components and schematic as well as PCB design. Third, the gateware was developed. In this part, the drivers, communication IPs and signal processing IPs are simulated and tested as well. Last but not least, the tests and measurements for the new system are done and compared to the old one