Simulated annealing (SA) is a popular iterative heuristic used to solve a wide variety of combinatorial optimization problems. However, depending on the size of the problem, it may have large run-time requirements. One practical approach to speed up its execution is to parallelize it. In this paper we develop parallel SA schemes based on the asynchronous multiple-Markov chain model (AMMC) described in S.-Y. Lee and K. G. Lee (1996) and applied to standard-cell placement as presented in J. Chandy et al. (1997), The schemes are applied to solve the multi-objective standard cell placement problem using an inexpensive cluster-of-workstations environment. This problem requires the optimization of conflicting objectives (interconnect wire-length,...
114 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1993.As the size of modern VLSI ci...
Simulated Evolution (SimE) is an evolutionary metaheuristic that has produced results comparable to ...
Cell placement is an important phase of current VLSI circuit design styles such as standard cell, ga...
Simulated annealing (SA) is a popular iterative heuristic used to solve a wide variety of combinator...
Simulated Annealing (SA) is a popular iterative heuristic used to solve a wide variety of combinator...
Simulated Annealing (SA) is a popular iterative heuristic used to solve a wide variety of combinator...
Simulated Annealing (SA) is a popular iterative heuristic used to solve a wide variety of combinator...
As modern VLSI designs have become larger and more complicated, the computational requirements for d...
Simulated Evolution (SimE) is a sound stochastic approximation algorithm based on the principles of ...
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a c...
Abstract — Simulated Evolution (SimE) is a sound stochastic approximation algorithm based on the pri...
Abstract-Parallel algorithms with quality equivalent to the simu-lated annealing placement algorithm...
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a c...
Simulated annealing is a general purpose Monte Carlo optimization technique that was applied to the ...
114 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1993.As the size of modern VLSI ci...
Simulated Evolution (SimE) is an evolutionary metaheuristic that has produced results comparable to ...
Cell placement is an important phase of current VLSI circuit design styles such as standard cell, ga...
Simulated annealing (SA) is a popular iterative heuristic used to solve a wide variety of combinator...
Simulated Annealing (SA) is a popular iterative heuristic used to solve a wide variety of combinator...
Simulated Annealing (SA) is a popular iterative heuristic used to solve a wide variety of combinator...
Simulated Annealing (SA) is a popular iterative heuristic used to solve a wide variety of combinator...
As modern VLSI designs have become larger and more complicated, the computational requirements for d...
Simulated Evolution (SimE) is a sound stochastic approximation algorithm based on the principles of ...
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a c...
Abstract — Simulated Evolution (SimE) is a sound stochastic approximation algorithm based on the pri...
Abstract-Parallel algorithms with quality equivalent to the simu-lated annealing placement algorithm...
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a c...
Simulated annealing is a general purpose Monte Carlo optimization technique that was applied to the ...
114 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1993.As the size of modern VLSI ci...
Simulated Evolution (SimE) is an evolutionary metaheuristic that has produced results comparable to ...
Cell placement is an important phase of current VLSI circuit design styles such as standard cell, ga...