FPGA Implementation of an Online Free-Space Optical Communications Test-Bed

Free Space Optical (FSO) satellite communications is proving to be a key enabling technology for global connectivity with the ability to provide connection across Europe with only 12 ground stations. For this, Deutsches Zentrum für Luft- und Raumfahrt (DLR) is working on implementing a robust communication system for FSO on a Xilinx RFSoC Field Programmable Gate Array (FPGA)(ZU28DR). However, FSO is susceptible to deep fades and atmospheric turbulence affecting the quality of the communication system. Thus, measuring the performance of the communication system is crucial for choosing system parameters and designing new blocks to enhance the performance. In this thesis, a high speed test-bed implementation exploiting Parallel Pseudo Random Binary Sequence (PRBS) to measure the performance of the system is implemented. The test-bed is designed to mitigate channel fading problems to correctly calculate the Bit Error Rate (BER). The test-bed is designed to allow for online adjustment of the communication system to facilitate parameter optimizations