A Research-Fertile Co-Emulation Framework for RISC-V Processor Verification

Thesis (Master's)--University of Washington, 2023As processor design complexities increase, so do their verification complexities. As a consequence, processor verification has slowed down and become less reliable. The recent drift towards agile chip design philosophies and increasingly expensive ramifications of bugs and security vulnerabilities only aggravate the situation. Despite advancements in expensive commercial verification solutions, there is still a need for cost-effective, fast and high-confidence open-source verification solutions. Automated verification methodologies have emerged as promising candidates for their speed and reliability; however, automation comes with its fair share of open problems -- which an inexpensive, easy-to-setup, and modifiable experimentation platform can help research. This thesis presents an open-source framework for FPGA-accelerated co-emulation of RISC-V processors. The framework is highly cost-effective, customizable, and scalable to FPGA-clusters, and has been field-tested against the silicon-validated BlackParrot processor, resulting in the discovery of 4 designer-acknowledged microarchitectural bugs. The framework offers a novel implementation of automated coverage instrumentation, a customizable FPGA shell for coverage and trace extraction, and FPGA-accelerated cosimulation which achieves a speedup of over 2000x against a popular RTL simulator. The thesis discusses key insights from the coverage effected by popular benchmarks and randomly generated programs in the context of BlackParrot