We present the measurements of matching and high count rate performance of a 64 channel readout ASIC called DEDIX for high count rate position-sensitive measurements using semiconductor detectors. The ASIC is designed in 0.35 mum CMOS process and its total area is 3900 times 5000 mum2. The DEDIX has a binary readout architecture. Each channel is built of a charge sensitive amplifier (CSA) with a pole-zero cancellation circuit, a shaper, two independent discriminators and two independent 20-bit counters. The size of the input device in CSA has been optimized for a detector capacitance in the range of 1-3 pF per strip. An equivalent noise charge of 110 el rms has been achieved for a total detector capacitance of 1 pF at the shaper peaking tim...