An analog VLSI implementation of one-class support vector machine for multiclass classification of highly dimensional vectors

A one-class support vector machine (OC-SVM) is implemented using an on-chip-trainable analog VLSI processor. The one-class classification of highly dimensional sample vectors can be solved with this analog processor. Since the OC-SVM learning mechanism is complicated, a special solution scheme for the learning operation is proposed on the basis of analog computational circuitries and a fully parallel architecture. In this manner, the built VLSI processor achieves a high learning speed and a compact chip area at the same time. By combining multiple OC-SVM processors, multiclass recognition can be implemented with an arbitrary number of classes. The proof-of-concept chip is fabricated for the recognition of 64-dimensional vectors representing real image patterns. Three OC-SVM processors are combined for three classes of samples, where all the on-chip learning operations are accomplished within 0.6 µs. From the measurement results, all the test patterns are correctly recognized or rejected by the recognition system built