As well as the schedule affects system performance, the control skew, i.e., the arrival time difference of control signals between registers, can be utilized for improving the system performance, enhancing robustness against delay variations, etc. The simultaneous optimization of the control step assignment and the control skew assignment is more powerful technique in improving performance. In this paper, firstly, we prove that, even if the execution sequence of operations which are assigned to the same resource is fixed, the simultaneous optimization problem under a fixed clock period is NP-hard. Secondly, we propose a heuristic algorithm for the simultaneous control step and skew optimization under given clock period, and we show how much...
A strategy to enhance the speed and power characteristics of an industrial circuit is demonstrated i...
Various optimizations and trade-offs have been implemented in synthesis systems. However, the clocki...
Many design techniques have been proposed to optimize the performance of a digital system implemente...
The choice of a clock period in designs with multicycle operations have a major influence on operato...
Skew optimization is an important stage of the physical design. Previous studies suggested various s...
This paper analyzes the effect of resource sharing and assignment on the clock period of the synthes...
Abstract — This paper investigates methods for minimizing the impact of process variation on clock s...
Clock synthesis, a crucial design step for high-performance VLSI circuits, has been extensively stud...
As the feature size of transistors becomes smaller, delay variations become a serious problem in VLS...
In a synchronous clock distribution network with negligible skews, digital circuits switch simultane...
This paper investigates the application of simultaneous retiming and clock scheduling for optimizing...
The paper considers the implementation of digital controllers as real-time tasks in priority-preempt...
We propose a fast clock skew scheduling algorithm which minimizes clock period and enlarges the slac...
In this paper, we propose an effective asynchronous datapath synthesis system to optimize statistica...
This paper analysis control computation latency and jitter, which have been largely ignored in the c...
A strategy to enhance the speed and power characteristics of an industrial circuit is demonstrated i...
Various optimizations and trade-offs have been implemented in synthesis systems. However, the clocki...
Many design techniques have been proposed to optimize the performance of a digital system implemente...
The choice of a clock period in designs with multicycle operations have a major influence on operato...
Skew optimization is an important stage of the physical design. Previous studies suggested various s...
This paper analyzes the effect of resource sharing and assignment on the clock period of the synthes...
Abstract — This paper investigates methods for minimizing the impact of process variation on clock s...
Clock synthesis, a crucial design step for high-performance VLSI circuits, has been extensively stud...
As the feature size of transistors becomes smaller, delay variations become a serious problem in VLS...
In a synchronous clock distribution network with negligible skews, digital circuits switch simultane...
This paper investigates the application of simultaneous retiming and clock scheduling for optimizing...
The paper considers the implementation of digital controllers as real-time tasks in priority-preempt...
We propose a fast clock skew scheduling algorithm which minimizes clock period and enlarges the slac...
In this paper, we propose an effective asynchronous datapath synthesis system to optimize statistica...
This paper analysis control computation latency and jitter, which have been largely ignored in the c...
A strategy to enhance the speed and power characteristics of an industrial circuit is demonstrated i...
Various optimizations and trade-offs have been implemented in synthesis systems. However, the clocki...
Many design techniques have been proposed to optimize the performance of a digital system implemente...