A 6K-Gate GaAs Gate Array with a New Large-Noise-Margin SLCF Circuit

A 6K-gate GaAs gate array has been successfully designed and fabricated using a new large-noise-margin Schottky-diode level-shifter capacitor-coupled FET logic (SLCF) circuitry and a WN_x-gate self-aligned LDD structure GaAs MESFET process. Chip size was 8.0×8.0 mm^2. A basic cell can be programmed as an SLCF inverter, a two-input NOR, or a two-input NAND gate. The unloaded propagation delay time was 76 ps/gate at a 1.2-mW/gate power dissipation. The increases in delay time due to various loading capacitances were 10 ps/fan-in, 45 ps/fan-out, and 0.64 ps/fF. A 16-bit serial-to-parallel-to-serial (S/P/S) data-conversion circuit was constructed on the gate array as an application example. A maximum operation frequency of 852 MHz was achieved at a 952-mW power dissipation, including I/O buffers