In this paper, we propose an effective asynchronous datapath synthesis system to optimize statistical performance of asynchronous systems. The proposed algorithm is a heuristic method which simultaneously performs scheduling and resource binding. During the design process, decisions will be made based on the statistical schedule length analysis. It is demonstrated that asynchronous datapaths with the reduced mean total computation time are successfully synthesized for some datapath synthesis benchmarks
Basic concepts for scheduling algorithms and control synthesis in high-level synthesis of asynchrono...
Various aspects of the two major tasks in high-level synthesis, scheduling and allocation, are studi...
We present a method for analyzing the time performance of asynchronous circuits, in paxticulax, thos...
In an asynchronous system, initiation and completion of operations are events that can occur at any ...
A new heuristic scheduling algorithm for time constrained datpath synthesis is described. The algori...
This paper presents an approach to generating asynchro nous schedules of various concurrency levels...
In this paper, we propose a new heuristic scheduling algorithm based on the statistical analysis of ...
Journal ArticleThis paper describes a new method for architectural synthesis of timed asynchronous s...
This paper presents a model and a method for the allocation during the high level datapath synthesis...
Traditional High-Level Synthesis (HLS) techniques do not allow reuse of complex, realistic datapath ...
Behavioral synthesis of synchronous systems is a well established and researched area. The transform...
We present a method for analyzing the timing performance of asynchronous circuits, in particular, th...
The objective of this work is to develop a new methodology for behavioural synthesis using a flow of...
Asynchronous or clockless design is believed to hold the promise of alleviating many of the challeng...
As witnessed by their recent rapid market growth, reconfigurable multi-functional data paths are an ...
Basic concepts for scheduling algorithms and control synthesis in high-level synthesis of asynchrono...
Various aspects of the two major tasks in high-level synthesis, scheduling and allocation, are studi...
We present a method for analyzing the time performance of asynchronous circuits, in paxticulax, thos...
In an asynchronous system, initiation and completion of operations are events that can occur at any ...
A new heuristic scheduling algorithm for time constrained datpath synthesis is described. The algori...
This paper presents an approach to generating asynchro nous schedules of various concurrency levels...
In this paper, we propose a new heuristic scheduling algorithm based on the statistical analysis of ...
Journal ArticleThis paper describes a new method for architectural synthesis of timed asynchronous s...
This paper presents a model and a method for the allocation during the high level datapath synthesis...
Traditional High-Level Synthesis (HLS) techniques do not allow reuse of complex, realistic datapath ...
Behavioral synthesis of synchronous systems is a well established and researched area. The transform...
We present a method for analyzing the timing performance of asynchronous circuits, in particular, th...
The objective of this work is to develop a new methodology for behavioural synthesis using a flow of...
Asynchronous or clockless design is believed to hold the promise of alleviating many of the challeng...
As witnessed by their recent rapid market growth, reconfigurable multi-functional data paths are an ...
Basic concepts for scheduling algorithms and control synthesis in high-level synthesis of asynchrono...
Various aspects of the two major tasks in high-level synthesis, scheduling and allocation, are studi...
We present a method for analyzing the time performance of asynchronous circuits, in paxticulax, thos...