Design and Implementation of a Fully Asynchronous SFQ Microprocessor: SCRAM2

A microprocessor test vehicle was developed for the investigation of asynchronous design methodology for rapid-single-flux-quantum (RSFQ) circuits. We have designed and implemented a fully asynchronous RSFQ microprocessor, named SCRAM2. The data-driven self-timing (DDST) architecture is used for the design of circuit blocks of the SCRAM2. In order to ensure the logical ordering between the circuit blocks, bit-serial handshaking was adopted. The performance of the handshaking system was enhanced based on the scalable-delay-insensitive (SDI) model. The SCRAM2 is an 8-bit bit-serial microprocessor with three-stage pipelining, with a basic microarchitecture similar to that of our previously designed synchronous microprocessor, CORE1 alpha. The estimated average performance of the SCRAM2 is 577 MIPS using a logic simulation. We have implemented all circuit components using the SRL 2.5 kA/cm(2) Nb process and confirmed their correct operation. Several operations of the SCRAM2 have been successfully confirmed