Novel serial–parallel converter using SFQ logic circuits

We have designed, fabricated and tested a time-to-digital converter (TDC) using SFQ logic circuits. The proposed TDC consists of two sets of ring oscillators and binary counters, and a coincidence detector (CD), which detects the coincidence of the arrival of two SFQ pulses from two ring oscillators. The advantage of the proposed TDC is its simple circuit structure with wide measurement range in addition to the high resolution and the high sensitivity of the SFQ TDC compared to semiconductor TDCs. The time resolution of the proposed TDC is limited by the resolution of the CD. In order to improve the resolution, we have developed a dynamic AND (DAND) gate, which can detect two simultaneous SFQ signal inputs with high accuracy. It was demonstrated that the time resolution of the TDC using the DAND gate is improved to be ±4 ps