Analysis of common-mode noise on on-chip differential lines through stochastic modeling of parameter variability

In this contribution a novel stochastic modeling strategy to analyze the influence of parameter variability on differential signaling over on-chip interconnects is presented. The method starts from an accurate computation of the differential line's per unit of length transmission line parameters, adopts a parameterized macromodeling scheme, and invokes the so-called stochastic Galerkin method (SGM). Parameter variability of the line itself and of the terminations are studied and compared to a traditional Monte Carlo (MC) approach, as such demonstrating excellent accuracy and efficiency of the proposed new technique. For the first time, an SGM is constructed for and applied to differential on-chip interconnects, and it is illustrated that this novel stochastic modeling strategy is very well suited to analyze common-mode noise induced by random imbalance of the line's terminations.In this contribution a novel stochastic modeling strategy to analyze the influence of parameter variability on differential signaling over on-chip interconnects is presented. The method starts from an accurate computation of the differential line's per unit of length transmission line parameters, adopts a parameterized macromodeling scheme, and invokes the so-called stochastic Galerkin method (SGM). Parameter variability of the line itself and of the terminations are studied and compared to a traditional Monte Carlo (MC) approach, as such demonstrating excellent accuracy and efficiency of the proposed new technique. For the first time, an SGM is constructed for and applied to differential on-chip interconnects, and it is illustrated that this novel stochastic modeling strategy is very well suited to analyze common-mode noise induced by random imbalance of the line's terminations.P