A simple model of EMI-induced timing jitter in digital circuits, its statistical distribution and its effect on circuit performance

A simple model has been developed to characterize electromagnetic interference induced timing variations (jitter) in digital circuits. The model is based on measurable switching parameters of logic gates, and requires no knowledge of the internal workings of a device. It correctly predicts not only the dependence of jitter on the amplitude, modulation depth and frequency of the interfering signal, but also its statistical distribution. The model has been used to calculate the immunity level and bit error rate of a synchronous digital circuit subjected to radio frequency interference, and to compare the electromagnetic compatibility performance of fast and slow logic devices in such a circuit