Mixed-signal Processing Techniques for RF Transmitters

The design of high performance integrated radio frequency (RF) transmitters (TX) able to meet the constant demand for faster, “greener”, and more cost-effective wireless communication links, is driving innovation on all fronts: device, circuit, and system level. Recent advances in advanced CMOS process nodes are pushing for more “digital-intensive” architectures, yet certain aspects of analog integrated circuits (ICs) cannot be easily replaced by digital functions. This thesis aims to take a fresh approach at the circuit and system level by proposing two designs that lie at the border between digital and analog domains. The first part of the thesis focuses on the design of a wireless TX front end based on the concept of time-variant passive signal processing. The digital-to-analog converter (DAC) is merged with a higher order passive switched-capacitor filter (PSCF) and so the functionalities of digital-to-analog conversion, baseband filtering, and signal upconversion are implemented by a passive switched capacitor (PSC) network. The resulting passive switched-capacitor DAC (PSC-DAC) offers a versatile architecture that fully benefits from CMOS scaling. The front end was integrated in a 65nm CMOS technology and can support various channel bandwidths simply by adjusting the switching frequency for the PSC network. Thanks to its third-order reconfigurable filter, it maintains a thermal noise floor better than −156 dBc/Hz at a power dissipation of 45 mW. The measured prototype achieves an alternate adjacent channel leakage ratio (ACLR2) of −57 dB and an error vector magnitude (EVM) of −31 dB for a 20-MHz 64-QAM OFDM and a 20-MHz 16-QAM signal,respectively. In the second part, quantized analog (QA) signal processing is applied for the first time in RF power amplification culminating in the concept of the quantized analog power amplifier (QA-PA). By allowing the signal to virtually exceed the supply, the QA-PA leads to an improvement in the output dynamic range that is not possible by conventional analog techniques. Simulations of a 65nm CMOS design show good agreement with the presented theory and predict up to 18dB improvement in both EVM and adjacent channel leakage ratio (ACLR) compared to an analog class-A poweramplifier (PA) for a 256-QAM, 100MHz 5G signal.Ph.D