Architecture and Automation for Efficient Convolutional Neural Network Acceleration on Field Programmable Gate Arrays

This thesis explores Convolutional Neural Network (CNN) inference accelerator architecture for FPGAs. We compare and contrast three high-level architectures, and elect to build a layer-pipelined design that leverages custom hardware for every layer in a CNN, and can skip zero-valued weights. While this increases the algorithmic execution efficiency, we find it makes it challenging to achieve a high operating frequency. To address this, we designed latency insensitive hardware templates that build a model of signal fanout and span and instantiate different structures within each compute unit to ensure a high operating frequency regardless of CNN topology. Together these optimizations enable throughput on a sparse Resnet-50 model at a batch size of 1 of 4550 images/s, which is nearly 4x the throughput of NVIDIA's fastest machine learning targeted GPU, the V100, and outperforms all prior work on FPGAs.M.A.S