Compact Area and Performance Modelling for Coarse-grained Reconfigurable Architectures

We consider area and performance modelling for coarse-grained reconfigurable architectures (CGRAs) and extend the open-source CGRA-ME (CGRA modelling and exploration) framework to rapidly estimate these metrics. Area is modelled by synthesizing commonly occurring CGRA primitives in isolation, and then aggregating the primitives' component-wise areas. Performance is modelled by integrating a static-timing analysis (STA) framework into CGRA-ME. The delays in the STA timing graph are based on component-wise delays, as well as estimated interconnect delay. Experimental results using the estimation engine demonstrate reasonably accurate estimation for both area and performance for different CGRA architectures, as well as different variations of the same architecture. By offering fast and accurate estimation in an early phase of CGRA architecture exploration, the estimation engine allows the user to bypass the lengthy process of a full VLSI implementation, and rapidly explore the area/performance architecture space.M.A.S