On-Chip Jitter Measurement and Mitigation Techniques for Clock and Data Recovery Circuits

This thesis describes three contributions in the area of on-chip jitter measurement and characterization, which can be used to help optimize the performance of wireline transceivers. Two on-chip jitter measurement techniques are developed and demonstrated, along with an adaptive loop gain CDR, which characterizes jitter on-chip to optimize its jitter tolerance. In the first measurement technique, the absolute jitter of random data is measured on-chip by correlating the phase detector outputs of two 10Gb/s CDRs locked to the same data. This technique allows the jitter's autocorrelation function to be estimated, from which the jitter's RMS value and power spectral density are extracted without using any external reference clock. Correlating the phase detectors in the CDRs with a third phase detector, which measures the phase difference between the clocks recovered by the two CDRs, allows measurement of the absolute recovered clock jitter. A test chip fabricated in 65nm CMOS demonstrates that this scheme can measure RMS jitter with sub-picosecond accuracy. To demonstrate the usefulness of on-chip jitter characterization in improving CDR performance, a loop gain adaptation strategy is proposed, which optimizes the jitter tolerance of a 28Gb/s PI-based CDR. The technique increases the CDR's loop gain to suppress the most jitter while monitoring the autocorrelation function of the bang-bang PD output to prevent the CDR from becoming too underdamped. The proposed technique requires no prior knowledge of the CDR's latency or jitter characteristics and can also be extended to operate in the presence of sinusoidal jitter. The concept is demonstrated in a test chip fabricated in 28nm CMOS. Lastly, a second jitter measurement technique is proposed, which estimates the relative jitter between the input data and recovered clock of a 28Gb/s half-rate digital PI-based CDR without using an eye monitor. Square wave jitter with a known amplitude is injected into the CDR, by adding a corresponding signal to the CDR's PI code. By measuring the effect of the injected jitter on the autocorrelation function of the CDR's bang-bang PD output, the RMS relative jitter is estimated with sub-picosecond accuracy. The scheme is demonstrated in the same 28nm test chip described above.Ph.D.2018-11-03 00:00:0