Improved Phase Detection for Digital Phase-locked Loops

Digital PLLs (DPLLs) have emerged as reliable alternatives to analog PLLs since they are more robust in the presence of process variations and mismatch and do not need a large on-chip capacitor to realize a loop filter. However, a DPLL employs a time to-digital converter (TDC) to resolve the phase error in quantized steps which shows up as deterministic jitter in the output clock. Similarly, a DPLL tunes a digitally controlled-oscillator (DCO) in discrete frequency steps which adds an extra source of jitter. Furthermore, the quantized response of the DPLL may cause chaotic limit cycles in some configurations. This thesis presents innovations to make DPLLs suitable for a wide range of applications. First, a novel low-power TDC with 4 ps resolution, approximately an order of magnitude better than an inverter delay in the 0.13 µm CMOS technology, is enabled by employing a highly digital coarse-fine TDC with a calibrated coarse stage followed by a fine stochastic stage. On power-up, on-chip calibration algorithm based on a balanced mean code density test is used to minimize nonlinearities in the coarse TDC, reducing worst-case spurs from -54.4 dBc to -70.55 dBc at 1.995 GHz operation. The thesis also investigates dead-zone behavior in DPLLs caused by the quantization effect of the TDC. It results in chaotic limit cycle behavior; producing higher than expected in-band phase noise and strong spurious tones. To alleviate this problem, a noise-shaped offset is added to the phase error to keep the TDC active and away from the dead-zone. The proposed solution is demonstrated in a 0.13 µm CMOS prototype achieving consistent low in-band noise. A binary bang-bang phase detector (BBPD) is a commonly used alternative to the power hungry TDC. However, BBPD based DPLLs have limited frequency pull-in and capture range that are traded off for steady-state jitter performance. The thesis proposes an alternative to BBPD by using a multi-phase bang-bang detector (MPBBD). Also, the thesis presents a rigorous mathematical analysis of the cycle slipping behavior to quantify the pull-in and capture range as well as the locking time for DPLL with either BBPD or MPBBD. The final formula gives a useful insight into the effect of various loop parameters on the cycle slipping behavior. A DPLL architecture with a MPBBD is presented and implemented in 28 nm CMOS technology to improve the pull-in and capture range while not affecting the steady-state jitter performance.Ph.D.2017-10-17 00:00:0