The Role of Voltage Regulation in Power Integrity for Multi-Gbps Parallel I/O Interfaces

Strategies for power supply distribution in high speed I/O interfaces including the design of low dropout regulators (LDOs) and allocation of decoupling capacitance are proposed to minimize power supply induced jitter (PSIJ) in load circuits (aggressors and victim circuits) sharing the same supply. Different LDOs should be used for the aggressor and victim circuits and it is preferable to allocate available decoupling capacitance to the aggressor circuit. A prototype is developed in 28nm CMOS with the aggressors - 4 transmitters (aggressors) and the victim circuit - 1 injection locked oscillator (ILO) sharing a common supply but operating under separate LDOs. LDO1 employs a conventional topology with a bandwidth of 10MHz for the transmitters and LDO2 employs tri-loop topology with a worst-case PSR of -15dB at 400MHz for the ILO. The resulting simulated transmitter jitter is 3.5ps-pp at 20Gbps and the ILO jitter is 710fs-pp at 10GHz.M.A.S