Synthesizable FPGA Fabrics

With increasing effort required for custom layout in deep-submicron technologies, we consider implementing field-programmable gate arrays (FPGAs) using standard cells. First, we extend the open-source Verilog-to-Routing (VTR) FPGA architecture evaluation framework to generate synthesizable Verilog for its architectural device model. Verilog can then be synthesized into standard cells, placed and routed using application-specific integrated circuit (ASIC) design tools. A second extension to VTR generates a configuration bitstream, used to configure the FPGA with user's circuit. The proposed framework and methodology opens the door to silicon implementation of a wide range of VTR-modelled FPGA fabrics. In an experimental study, several FPGA implementations synthesized in 65nm TSMC standard cells are compared with a 65nm Altera commercial FPGA. Finally, we consider augmenting the generic standard-cell library from TSMC with a manually designed and laid-out FPGA-specific cell. We demonstrate the utility of the custom cell in reducing the area of the synthesized FPGA fabric.M.A.S