Front-end Building Blocks for 100+ GS/s ADCs

In this thesis IC building blocks for future 100+Gbaud fiber-optic receivers, employing high-speed ADC converters above 100 GSps, are investigated. A single-ended broadband, low-noise amplifier was designed in a 55nm SiGe BiCMOS technology. The DC-92GHz amplifier consumes 48 mW from a 2.3V supply and achieves 13 dB of gain and a noise figure of 6 dB up to 88 GHz. The circuit was measured to operate correctly up to 120 Gbps. To the best of the author's knowledge, this is the lowest noise amplifier in any technology ever tested at this data rate. A high-speed track-and-hold amplifier (THA) was designed in the same technology for time-interleaved 100+GS/s ADCs. It can support 90GS/s operation (was tested up to 108GS/s), has 40GHz input bandwidth, and consumes 87 mW from 1.8V and 2.5V supplies, delivering record-breaking performance among previously published high-speed THAs.M.A.S