High Performance Branch Predictors For Soft Processors

Branch prediction has been extensively studied in the context of application specific custom logic (ASIC) implementations. However, naively porting ASIC-based branch predictors to FPGAs may prove slow and/or resource-inefficient. Accordingly, this work studies the FPGA implementation of several commonly used branch predictors and does so in the context of simple pipelined processors, the most commonly used general purpose soft processor architecture. It assumes a processor implementation representative of Altera's Nios II-f and investigates the performance and resource cost of various branch predictors. The analysis confirms that existing designs are not efficient nor high-performing on reconfigurable logic. Accordingly, this work proposes FPGA-specific modifications that improve accuracy and resource cost. Finally, this work proposes a minimalistic branch predictor gRselect with the hardware budget on par with Nios II-f, as well as an overriding TAGE predictor O-TAGE-SC that delivers the highest performance among all the considered branch prediction schemes.M.A.S