Mixing buffers and pass transistors in FPGA routing architecture

grantor: University of TorontoFPGAs have become one of the most popular implementation media for digital circuits. Compared to regular full-fabricated integrated circuits, FPGAs have a huge time-to-market advantage. This is because FPGAs can be programmed in seconds versus regular ICs take months to fabricate. However, circuits implemented in FPGAs are typically three times slower than those implemented in regular full-fabricated ICs and about one-tenth of the density of circuits implemented in full-fabricated ICs. Most of the speed and area penalty is due to programmable routing resources contained in the FPGA. Therefore, the design of a good routing architecture is crucial to achieve system performance and density. In this thesis, we focus on the design of the inter-cluster routing topology. Previous inter-cluster routing topology prevents buffered routing tracks from connecting to pass transistor routing tracks. We present a new inter-cluster routing topology which allows liberal switching between buffered and pass transistor routing tracks. We show that one version of the new architecture results in 10% faster critical path delay yet requires same area as previous architectures.M.A.Sc