A high-speed chip to chip interconnection circuit for FPGA emulation systems

grantor: University of TorontoIn partitioned FPGA designs such as those in FPGA emulation systems, the limited number of I/0 pins typically restricts the amount of on-chip logic that can be used. This thesis describes a system that increases the amount of data transferred from chip to chip by multiplexing sixteen 8-bit wide on-chip signals at 100MHz into a 12-bit wide off-chip signal that operates at 1.6Gbps per pin. The transmitted data is encoded so that each set of transmitted bits is dc-balanced and contains guaranteed transitions which the receiver uses to track changes in the timing of the data. The sampler timing in each of the receivers is dynamically adjusted to account for any pin-to-pin timing skew. The encoder, transmitter and receiver were implemented in a 0.35[mu]m CMOS process. Simulations show that will transmit and receive data at a rate of 1.6Gbps per pin.M.A.Sc