Memory interfacing for the OneChip reconfigurable processor

grantor: University of TorontoWhile previous custom compute machines claim to offer high performance, they all suffer from a slow interconnection architecture between the logic and memory. This thesis describes the architecture of a custom compute machine that overcomes the interconnection bottleneck by closely integrating a fixed logic processor, a reconfigurable logic array, and memory into a single chip, called OneChip. The OneChip system has a seamless programming model that enables the programmer to easily specify instructions without complex instruction decoding. To allow the processor and the reconfigurable array to execute concurrently, the programming model ensures that memory consistency is maintained. To evaluate the feasibility of the OneChip architecture, a 32-bit MIPS-like processor and several performance enhancement applications were mapped to the Transmogrifier-2 field programmable system. For two typical applications, the 2-dimensional discrete cosine transform and the 64-tap FIR filter, we were capable of achieving a performance speedup of over thirty times that of a stand-alone state-of-the-art processor.M.A.Sc