Design of a programmable switched-capacitor analog FIR filter

grantor: University of TorontoThe use of an analog adaptive filter can offer benefits over a digital adaptive filter in application that require high-speed, low-power, and a moderate degree of linearity. An adaptive digital FIR filter will typically be implemented as a finite impulse response filter using a pipelined tapped delay fine with programmable tap coefficients. When an analog adaptive filter is constructed, a parallel tapped delay line is used. A programmable analog FIR will typically use buffered sample-and-hold blocks for the analog delay line and transconductors to implement the MDACs used for the tap coefficient multiplication. The research focusses on a more passive approach to the circuit realization. An entirely voltage-mode, switched-capacitor implementation is presented. A seven tap adaptive analog FIR filter using the passive architecture is realized in an area of 1.44mm2. The fabricated chip has a power dissipation of 104mW using a sampling frequency of 200MHz and a power supply of 3.3V.M.A.Sc