Application-specific instruction-set architectures for embedded DSP applications

grantor: University of TorontoProgrammable digital signal processors (DSPs) are microprocessors with specialized architectural features for the efficient execution of digital signal processing algorithms at relatively low cost. These features also make DSPs difficult targets for high-level language (HLL) compilers, and require that assembly language programming be used to fully exploit their capabilities. As applications become larger and more complex, and as design cycles are required to be shorter, it is important to move towards using more HLL programming. To achieve this, more compiler-friendly DSP architectures and better DSP compiler technology are required. As DSP cores become more pervasive in embedded system-on-a-chip designs, a need is also emerging for application-specific DSP cores that can be customized to the functional, performance, and cost requirements of a target application, or group of applications. This dissertation examines the use of VLIW architectures to achieve a suitable compiler target while being able to express the forms of parallelism found in most DSP applications. Performance improvements by factors of 1.8-2.8 are shown to be achievable simply by using a VLIW architecture compared to more traditional architectures. A method for reducing the instruction bandwidth and storage requirements of VLIW architectures is also proposed, and its impact on performance and cost is examined. To handle some of the DSP-specific architectural features, an optimizing C compiler is developed. In particular, two algorithms that enable the compiler to allocate data automatically across dual data-memory banks are developed, and their impact on cost and performance are examined. Finally, a set of tools that enable a designer to customize the architecture and its instruction set to the requirements of a target application is also presented. This includes an area-estimation model and an instruction-set simulator for measuring cost and execution performance.Ph.D