Class E power amplifiers for wireless transceivers

grantor: University of TorontoThe thesis deals with the design of a Class E power amplifier in CMOS technology. Presently in wireless communication systems, the power amplifier is implemented in GaAs or bipolar technologies, while the signal processing blocks are done in CMOS. If the power amplifier could be implemented in CMOS, it would allow the system to be fabricated on a single chip, thus reducing power, area and cost. The objective of this thesis is to investigate the design of such an amplifier in a deep submicron CMOS process. A Class E amplifier configuration was selected for implementation due to its expected high efficiency. The Class E power amplifier was implemented in a 0.35 [mu]m standard CMOS technology. The modeling of the CMOS compatible inductors used in the amplifier was carefully considered. A modified scalable inductor model was developed based upon process parameters and the spiral characteristic. The integrated amplifier itself consisted of a Class F driver and a Class E power stage. The amplifier was successfully implemented, occupying a silicon area of 1.92 mm2. The amplifier operates at 835MHz, delivering 79mW of power to a 50[Omega] load from a 3.3V supply with a power added efficiency of 36%.M.A.Sc