Add to ORKGgrantor: University of TorontoThis thesis describes a novel approach for distributing low skew clock signals across large digital systems independent of environmental and process variations. The technique is integrated into a multi-output clock buffer circuit that can handle a scalable number of clock loads in a point-to-point configuration. The circuit contains an impedance-locked loop that continuously monitors the impedance of output clock traces and adjusts driver impedance for optimal matching. Reflections from clock destinations contain propagation delay information that is used by delay-locked loops to continuously adjust the departure time of outgoing clocks to ensure low relative skew at clock destinations. A theoretical ...
Resonant clocking is an attractive alternative to conventional clocking due to its significant poten...
Clock skew constraint satisfaction is one of the most important tasks in the clock network design, e...
This dissertation addresses timing and synchronization methodologies that are critical to the design...
grantor: University of TorontoThis thesis describes a novel approach for distributing low ...
Synchronous clock distribution continues to be the dominant timing methodology for very large scale ...
We propose a clock buffer that is able to compensate clock skews possibly due to process variations,...
In a synchronous clock distribution network with negligible skews, digital circuits switch simultane...
The thermal gradients existing in high-performance circuits may significantly affect their timing be...
The thermal gradients existing in high-performance circuits may significantly affect their timing be...
The thermal gradients existing in high-performance circuits may significantly affect their timing be...
[[abstract]]Clock skew optimization continues to be an important concern in circuit designs. To over...
The buffered clock tree structure is commonly used to distribute the clock signal to the memory elem...
This thesis investigates the use of averaging techniques in the development of clock ...
Power densities and temperatures in today's high performance circuits have reached alarmingly high l...
Power is a primary concern in modern circuits. Clock distribution networks, in particular, are an es...
Resonant clocking is an attractive alternative to conventional clocking due to its significant poten...
Clock skew constraint satisfaction is one of the most important tasks in the clock network design, e...
This dissertation addresses timing and synchronization methodologies that are critical to the design...
grantor: University of TorontoThis thesis describes a novel approach for distributing low ...
Synchronous clock distribution continues to be the dominant timing methodology for very large scale ...
We propose a clock buffer that is able to compensate clock skews possibly due to process variations,...
In a synchronous clock distribution network with negligible skews, digital circuits switch simultane...
The thermal gradients existing in high-performance circuits may significantly affect their timing be...
The thermal gradients existing in high-performance circuits may significantly affect their timing be...
The thermal gradients existing in high-performance circuits may significantly affect their timing be...
[[abstract]]Clock skew optimization continues to be an important concern in circuit designs. To over...
The buffered clock tree structure is commonly used to distribute the clock signal to the memory elem...
This thesis investigates the use of averaging techniques in the development of clock ...
Power densities and temperatures in today's high performance circuits have reached alarmingly high l...
Power is a primary concern in modern circuits. Clock distribution networks, in particular, are an es...
Resonant clocking is an attractive alternative to conventional clocking due to its significant poten...
Clock skew constraint satisfaction is one of the most important tasks in the clock network design, e...
This dissertation addresses timing and synchronization methodologies that are critical to the design...