Performance issues in the design of hierarchical-ring and direct networks for shared-memory multiprocessors

grantor: University of TorontoThis dissertation explores performance issues in the design of interconnection networks for shared-memory multiprocessors. In particular, it considers low-dimensional direct (e.g., mesh and tori) and hierarchical-ring networks, and studies issues in topology, buffer management, switching, routing and flow control. The performance evaluation is primarily done by simulating the target systems at the register transfer level on a cycle-by-cycle basis using both synthetic and real (SPLASH-2) workloads. The contributions of the dissertation include: (1) the first extensive performance study specifically for shared-memory multiprocessor interconnection networks. Prior research focused primarily on distributed memory systems. It is important to consider shared-memory systems separately because of the different class of traffic they must support. (2) the first extensive simulation study of hierarchical-ring networks. Topologies that perform well are derived, and various cut-through switching techniques, such as wormhole, virtual cut-through, cell switching are evaluated under both blocking and non-blocking flow control policies. (3) a comprehensive comparative performance study of 2D mesh, 2D tori and hierarchical-ring networks. It is shown that the hierarchical-ring networks outperform the mesh and tori networks for system sizes smaller than 64 processors. (4) a novel deadlock free routing technique for wormhole switched hierarchical-ring networks using a virtual channel approach. (5) a novel priority-based network design that uses dynamic virtual channels and prioritized link arbitration with priority inheritance that results in improved system throughput and can be used to support multiple classes of traffic.Ph.D