Power, Performance and Area Consequences of Multi-context Support in Coarse-grained Reconfigurable Arrays

Coarse-Grained Reconfigurable Arrays (CGRAs) are programmable logic devices comprising a two-dimensional array of large, often ALU-like, logic blocks, and datapath-style (multi-bit) programmable interconnect. A feature frequently associated with CGRAs is dynamic reconfigurability, wherein the CGRA supports multiple contexts. The multiple contexts form a set of configuration bitstreams that are loaded into the CGRA simultaneously and cycled through according to a schedule. Multi-context allows the CGRA hardware to be time-multiplexed: the logic blocks and interconnect can perform different functions according to the context selected in each clock cycle. In this thesis, we consider how multi-context may be implemented at the circuit level, and evaluate four circuit implementations from the power, performance, and area (PPA) perspectives. The PPA overhead of the multi-context feature in CGRAs vs. a single-context device is also quantified. We also explore context-switching using a State Transition Controller (STC), which can switch contexts without a fully predefined pattern.M.A.S