Add to ORKG(eng) This report addresses the problem of improving the execution performance of saturated reduction loops on fixed-point instruction-level parallel Digital Signal Processors (DSPs). We first introduce ``bit-exact'' transformations, that are suitable for use in the ETSI and the ITU speech coding applications. We then present ``approximate'' transformations, the relative precision of which we are able to compare. Our main results rely on the properties of the saturated arithmetic
Aggressive pipelining allows FPGAs to achieve high throughput on many Digital Signal Processing ap...
Graduation date: 1989Parallel solutions for two classes of linear programs are\ud presented. First w...
In the past decade, several tools have been developed to automate the floating-point to fixed-point ...
This report addresses the problem of improving the execution performance of saturated reduction loop...
Aggressive pipelining allows FPGAs to achieve high throughput on many Digital Signal Processing appl...
Developing efficient programs for many of the current parallel computers is not easy due to the arch...
. We discuss algorithms for global reduction (or combine) operations (e.g., global sums) for numbers...
A parallel program consists of sets of concurrent and sequential tasks. Often, a reduction (such as ...
A novel comprehensive and coherent approach for the purpose of increasing instruction-level parallel...
Software pipelining is a loop optimization technique used to speed up loop execution. It is widely i...
We detail an algorithm implemented in the R-Stream com-piler1 to perform controlled array expansion ...
Parallel bit stream algorithms exploit the SWAR (SIMD within a register) capabilities of commodity p...
Although programmable digital signal processors comprise a significant fraction of the processors so...
Architectures with instruction level parallelism such as VLIW and superscalar processors provide par...
This paper presents designs for parallel saturating multioperand adders. These adders have only a si...
Aggressive pipelining allows FPGAs to achieve high throughput on many Digital Signal Processing ap...
Graduation date: 1989Parallel solutions for two classes of linear programs are\ud presented. First w...
In the past decade, several tools have been developed to automate the floating-point to fixed-point ...
This report addresses the problem of improving the execution performance of saturated reduction loop...
Aggressive pipelining allows FPGAs to achieve high throughput on many Digital Signal Processing appl...
Developing efficient programs for many of the current parallel computers is not easy due to the arch...
. We discuss algorithms for global reduction (or combine) operations (e.g., global sums) for numbers...
A parallel program consists of sets of concurrent and sequential tasks. Often, a reduction (such as ...
A novel comprehensive and coherent approach for the purpose of increasing instruction-level parallel...
Software pipelining is a loop optimization technique used to speed up loop execution. It is widely i...
We detail an algorithm implemented in the R-Stream com-piler1 to perform controlled array expansion ...
Parallel bit stream algorithms exploit the SWAR (SIMD within a register) capabilities of commodity p...
Although programmable digital signal processors comprise a significant fraction of the processors so...
Architectures with instruction level parallelism such as VLIW and superscalar processors provide par...
This paper presents designs for parallel saturating multioperand adders. These adders have only a si...
Aggressive pipelining allows FPGAs to achieve high throughput on many Digital Signal Processing ap...
Graduation date: 1989Parallel solutions for two classes of linear programs are\ud presented. First w...
In the past decade, several tools have been developed to automate the floating-point to fixed-point ...