Improving the Performance of DRAM Memory Subsystem at Low Cost

Over the past years, driven by an increasing number of data-intensive applications, architects have proposed a variety of memory-centric strategies, e.g., processing-in-memory (PIM), near-data processing (NDP), and memory-based accelerators, to tackle the challenge of limited bandwidth and bridge the gap between computing and storage. We have seen their potential benefits of gaining significant improvement in performance and energy through myriad studies. However, we are still impeded by the increasing complexity/overhead of these memory-centric innovations. This is often in conflict with cost-sensitive memories, which have been deeply optimized for cost-per-bit. The objective of my study is to increase memory bandwidth or improve memory bandwidth efficiency at negligible or even zero cost. The primary approach is to boost resource utilization in memories, achieving overall efficiency without requiring expensive technology advancement. For example, memory designers often assign redundant resources to improve product yields or reduce design complexity, while many of these resources are left under-utilized in real products. The opportunity here is that we can exploit these latent resources for further performance boosting at no extra cost. In particular, my research was conducted from two perspectives: (1) recycling unused resources for better memory performance, and (2) repurposing engaged resources for new functionalities. To overcome bandwidth limitation, I propose a low-cost and compatible PIM design, termed ELP2IM, by repurposing DRAM arrays into active computation units. Specifically, bitlines and cells in an array are functioning as logic gates and registers, respectively. To improve bandwidth efficiency, I first advocate an efficient and lightweight design, termed SAM, which addresses the over-fetching problem faced by many in-memory database (IMDB) applications with strided access patterns. It exploits under-utilized internal bandwidth to filter more required data, so as to saturate the channel bandwidth. I further present a minimum-cost design, termed ReBACK, to mitigate the metadata challenge prevalent in numerous modern memory innovations. It recycles some hidden bandwidth in advanced ECC schemes by decoupling the process of error detection and error correction to amortize the metadata overhead. Unlike prior approaches that often directly modify memory structures, my proposal prioritizes the optimal utilization of existing resources with minimum additional hardware costs