Design and Implementation of Low Power High Speed 32-Bit HCSA

In the design of carry select adder, the requirement of area, speed and power consumption is of prime importance. Power dissipation is one of the most important design objectives in integrated circuits, after speed. Carry select adder (CSLA) is one of the fast adder used to perform fast arithmetic operations as we select the carry beforehand and calculate the sum output for both the carry conditions i.e. for Cin=1 or Cin=0. The most fundamental arithmetic operations in any ALU is addition. It has been ranked the most extensively used operation among a set of real-time digital signal processing benchmarks from application-specific DSP to general purpose processors [1]. Efficient utilization of CSLA depends upon the gate level modification. In this paper, 32-bit linear CSLA has been modified in such a way that the pipeline architecture that we have developed consumes minimum power as well as provide a high speed. In this project, the entire adder architecture has been implemented using VHDL and simulated using Mentor Graphics tool suite. The architecture is then further evaluated in FPGA using Xilinx ISE Design Suite