Bug Fixes fixed bug in WISHBONE interface: pipelined Wishbone mode did not clear STB after first transfer cycle Updates and New Features on-chip debugger: reworked JTAG signal input/output synchronization logic (#216) reworked TRNG (#212) :warning: removed WI_CTRL_CKSTEN flag (enable clock stretching) from control registers, clock-stretching is now always enabled major control unit and AKU logic optimizations; :lock: closed further illegal instruction encoding holes (system environment instructions, ALU and ALU-immediate instructions, FENCE instructions) (#204) :warning: reworked IRQ trigger logic of SPI, TWI, UART0, UART1, NELOED and SLINK; FIRQs now only trigger once when the programmed interrupt condition is met instead of triggering ...
What's Changed Fix some typos. by @ahmedcharles in https://github.com/stnolting/neorv32/pull/286 Fi...
What's Changed [setups] move to repo neorv32-setups by @umarcor in https://github.com/stnolting/neo...
This list shows the main core changes since the last release. See the project's changelog for more i...
What's Changed Fix neorv32_gpio_port_get() by @hipolitoguzman in https://github.com/stnolting/neorv...
What's Changed :sparkles: Add watchdog pause flag by @stnolting in https://github.com/stnolting/neo...
What's Changed [rtl] cycle & instret bug fix, wishbone.we bug fix; minor rtl updates by @stnolting...
This list shows the main core changes since the last release. See the project's changelog for more i...
This list shows the main core changes since the last release. See the project's changelog for more i...
Bug Fixes fixed bug in *_reduce_f VHDL functions (#186) fixed imprecise illegal instructions except...
What's Changed :warning: remove CPU's A ISA extension (atomic memory access) by @stnolting in https...
What's Changed :bug: fix CPU stall on illegal LD/ST instruction by @stnolting in https://github.com...
What's Changed Fix compile error with questa, for issue #242 by @tmeissner in https://github.com/st...
What's Changed ✨[Zxcfu ISA ext.] add option to implement custom RISC-V instructions by @stnolting i...
What's Changed [CFS] add another 64 interface registers by @stnolting in https://github.com/stnolti...
This list shows the main changes since the last release. See the project's changelog for more inform...
What's Changed Fix some typos. by @ahmedcharles in https://github.com/stnolting/neorv32/pull/286 Fi...
What's Changed [setups] move to repo neorv32-setups by @umarcor in https://github.com/stnolting/neo...
This list shows the main core changes since the last release. See the project's changelog for more i...
What's Changed Fix neorv32_gpio_port_get() by @hipolitoguzman in https://github.com/stnolting/neorv...
What's Changed :sparkles: Add watchdog pause flag by @stnolting in https://github.com/stnolting/neo...
What's Changed [rtl] cycle & instret bug fix, wishbone.we bug fix; minor rtl updates by @stnolting...
This list shows the main core changes since the last release. See the project's changelog for more i...
This list shows the main core changes since the last release. See the project's changelog for more i...
Bug Fixes fixed bug in *_reduce_f VHDL functions (#186) fixed imprecise illegal instructions except...
What's Changed :warning: remove CPU's A ISA extension (atomic memory access) by @stnolting in https...
What's Changed :bug: fix CPU stall on illegal LD/ST instruction by @stnolting in https://github.com...
What's Changed Fix compile error with questa, for issue #242 by @tmeissner in https://github.com/st...
What's Changed ✨[Zxcfu ISA ext.] add option to implement custom RISC-V instructions by @stnolting i...
What's Changed [CFS] add another 64 interface registers by @stnolting in https://github.com/stnolti...
This list shows the main changes since the last release. See the project's changelog for more inform...
What's Changed Fix some typos. by @ahmedcharles in https://github.com/stnolting/neorv32/pull/286 Fi...
What's Changed [setups] move to repo neorv32-setups by @umarcor in https://github.com/stnolting/neo...
This list shows the main core changes since the last release. See the project's changelog for more i...