Implementation of Turbo Coder Using Verilog HDL for LTE

In many communication systems, turbo codesare employed to repair errors. Turbo codes demonstrate high error correction when compared to other error correction methods. A Very Large Scale Integration is suggested in this study. VLSI architecture for the Turbo encoder implementation, Interleaves and de interleaves, and soft-in-soft-out decoders are employed. This study employs a technique that for the encoder portion, includes two recursive systematic convolutional (RSC) encoders , a Block interleaver and the decoder part involve Soft Output Virtebi Algorithm(SOVA) decoder. Aconvolutional code is a sort of error-correcting code used incommunicationsthat creates parity signals by sliding a Boolean polynomial function across a data stream. The word "convolutional coding" comes from the sliding application, which depicts the encoder's "convolution" acrossthe data. Convolutional codes sliding properties make it easier to do trellis decoding with a time-invariant trellis. Convolutional codes can be maximum-likelihood soft-decision decoded with a manageable level of complexity thanks to time invariant trellis decoding. The Viterbi algorithm, also known as the Viterbi path, is a dynamic programming approach for determining the greatest probability estimate of the most probable series of hidden states that leads to a series of observed events. The quantity of times needed to decode the bits is been reduced in this methodology. A block interleaver accepts a set of symbols and rearranges them, without repeating or omitting any of the symbols in the set. The number of symbols in each set is fixed for a given interleaver. Turbo encoding, as well as decoding simulations are done using Modelsim software