High-Performance Compute Board - A Fault-Tolerant Module for On-Boards Vision Processing

Cobham Gaisler, in collaboration with Ubotica Technologies, the National and Kapodistrian University of Athens, and QinetiQ Space, is developing a High-Performance Compute Board (HPCB) within the European Space Agency GSTP activity “FPGA Accelerated DSP Payload Data Processor Board”. Compared to existing technology, the HPCB platform will provide more computational resources onboard spacecrafts to process high bit-rate payload data before downlink, thus reducing bandwidth requirements and improving reaction times of space systems. The target applications include on-board payload processing for optical and radar instruments, as well as visual navigation. The board can be integrated in payload data handling units, mass-memory and/or on-board computer to enable functions such as high-performance on-board image processing, machine vision and standard CCSDS image compression. The board design is optimized for the data handling and processing of multiple instruments simultaneously. The architecture combines up to three Vision Processing Units (VPUs, Intel Movidius Myriad 2), a high-capacity FPGA (Xilinx Kintex Ultrascale XCKU060), and a radiation-tolerant microcontroller (Cobham Gaisler GR716), in order to create a reliable system solution for space applications that matches what is available in the commercial domain in terms of performance and functionality. The use of three VPUs and the parallel cores within each VPU leads to the high performance needed for image/application processing. The architecture targets a 6U by 160 mm Payload Module implemented according to the OpenVPX standard (VITA 65). The main board contains the microcontroller and the FPGA and supports the use of up to three VITA 57.1 FMC mezzanine cards. Each mezzanine contains a VPU and its associated power and memory components. The VPUs can be operated in parallel for maximum performance or redundant configurations. The main front-panel interfaces to operate the platform are four SpaceFibre links and two SpaceWire links. The SpaceFibre links nominally operate at 3.125 Gbps and are routed to the high-speed transceivers of the FPGA, whereas the SpaceWire links run at 100 Mbps and are routed to both FPGA and microcontroller via a cross-point-switch. Backplane interfaces are adapted to the OpenVPX standard and include SpaceWire for control and SpaceFibre for data. The board can also be operated stand-alone, equipped with debug links such as USB and JTAG intended for lab usage. The main board contains 2 SPI flash memories with the configuration files for the microcontroller, the FPGA and the VPUs. Additionally, it includes 2 DDR3 SDRAMs which operate as the working memory of the FPGA. This allows to buffer large amount of input images before they are processed by the VPUs. Each VPU has a dedicated 4GB DDR3 acting as its working memory. The HPCB is accompanied by software images for both the VPUs and the supervisor microcontroller. The VPU software exposes a unified API for image pre-processing functions and for Neural Network inference. End users can further expand the functionality of the board by procuring or developing new software for the VPUs. The integration testing of all hardware and software module is on-going and the HPCB is planned to be released in Q2/Q3 2021