We solve the two challenges architects face when designing heterogeneous processors with cache coherent shared memory. First, we develop an automated tool, called HeteroGen, for composing clusters of cores, each with its own coherence protocol. Second, we show that the output of HeteroGen adheres to a precisely defined memory consistency model that we call a compound consistency model. For a wide variety of protocols --- including the MOESI variants, as well as those that are targeted towards Total Store Order and Release Consistency --- we show that HeteroGen can correctly fuse them. To validate HeteroGen, we develop the first litmus tests for verifying that heterogeneous protocols satisfy compound consistency models. To understand the pos...
Modern HPC systems are becoming increasingly heterogeneous, affecting all components of HPC systems,...
Hierarchical Cache Consistency (HCC) is a scalable cache-con-sistency architecture for chip multipro...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...
Abstract We solve the two challenges architects face when designing heterogeneous processors with c...
Today’s mobile, desktop, and server processors are heterogeneous, consisting not only of CPUs but al...
Today's mobile, desktop, and server processors are heterogeneous, consisting not only of CPUs but al...
As the benefits from transistor scaling slow down, specialization is becoming increasingly important...
Weak memory consistency models can maximize system performance by enabling hardware and compiler opt...
The end of Dennard scaling and Moore's law has motivated a rise in the use of parallelism and hardwa...
The most commonly assumed memory consistency model for shared-memory multiprocessors is Sequential C...
In embedded system-on-a-chip (SoC) applications, the need for integrating heterogeneous processors i...
Computer architects are now studying a new generation of chip architectures that may integrate hundr...
In embedded system-on-a-chip (SoC) applications, the demand for integrating heterogeneous processors...
During the last few years many different memory consistency protocols have been proposed. These rang...
New generation System-on-Chips will be extremely complex devices, composed from complex subsystems, ...
Modern HPC systems are becoming increasingly heterogeneous, affecting all components of HPC systems,...
Hierarchical Cache Consistency (HCC) is a scalable cache-con-sistency architecture for chip multipro...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...
Abstract We solve the two challenges architects face when designing heterogeneous processors with c...
Today’s mobile, desktop, and server processors are heterogeneous, consisting not only of CPUs but al...
Today's mobile, desktop, and server processors are heterogeneous, consisting not only of CPUs but al...
As the benefits from transistor scaling slow down, specialization is becoming increasingly important...
Weak memory consistency models can maximize system performance by enabling hardware and compiler opt...
The end of Dennard scaling and Moore's law has motivated a rise in the use of parallelism and hardwa...
The most commonly assumed memory consistency model for shared-memory multiprocessors is Sequential C...
In embedded system-on-a-chip (SoC) applications, the need for integrating heterogeneous processors i...
Computer architects are now studying a new generation of chip architectures that may integrate hundr...
In embedded system-on-a-chip (SoC) applications, the demand for integrating heterogeneous processors...
During the last few years many different memory consistency protocols have been proposed. These rang...
New generation System-on-Chips will be extremely complex devices, composed from complex subsystems, ...
Modern HPC systems are becoming increasingly heterogeneous, affecting all components of HPC systems,...
Hierarchical Cache Consistency (HCC) is a scalable cache-con-sistency architecture for chip multipro...
Cache coherence is one of the main challenges to tackle when designing a shared-memory multiprocesso...