PSP is a well-known surface potential based model for deep-submicron bulk MOSFET. Initially, PSP model was grounded from MOS Model 11 (from NXP Semiconductors) and SP (from Pennsylvania State University and later at Arizona State University). In December 2005, PSP has been elected a new industrial standard model by the Compact Model Council (CMC). Since 2015, this model is jointly developed by NXP Semiconductors and CEA-Leti. In this presentation, we propose an overview of recent PSP versions with a focus on the latest developments about the charge model. The most recent version is PSP103.8. In this version, new models of the inner fringe charges and the inversion of overlaps have been introduced to improve the accuracy of the model for sho...
This paper reviews present compact model development and outlines the main features of the PUNISM, a...
This paper outlines the charge-based core and the model architecture of the BSIM5, an advanced charg...
With the continuous scaling of CMOS technologies, Silicon-on-Insulator (SOI) technologies have becom...
International audienceWith the maturity of CMOS technologies and their use for low voltage analog ap...
This paper outlines the advanced Surface-Potential-Plus (SPP) approach for the next generation CMOS ...
Charge-based and surface-potential-based models for undoped surrounding gate MOSFETs are compared fr...
Abstract — This paper reports recent progress on partially depleted (PD) SOI modeling using a surfac...
The accuracy of the existing metal-oxide-semiconductor-field-effect-transistor (MOSFET) models used ...
Abstract—This work describes an advanced physics-based com-pact MOSFET model (SP). Both the quasista...
In this paper, a small-signal MOSFET model is described, which takes the local effects of both veloc...
This paper reviews present compact model development and outlines the main features of the PUNISM, a...
Like other surface-potential based model, our surface-potential-plus model starts with charge-sheet ...
In this paper the capacitance components of the PSP compact model which is selected as successor of ...
This paper presents a new and more accurate potential based model for bulk MOSFET compared to the tr...
Abstract. This paper addresses current issues in compact MOSFET modeling, provides an overview and s...
This paper reviews present compact model development and outlines the main features of the PUNISM, a...
This paper outlines the charge-based core and the model architecture of the BSIM5, an advanced charg...
With the continuous scaling of CMOS technologies, Silicon-on-Insulator (SOI) technologies have becom...
International audienceWith the maturity of CMOS technologies and their use for low voltage analog ap...
This paper outlines the advanced Surface-Potential-Plus (SPP) approach for the next generation CMOS ...
Charge-based and surface-potential-based models for undoped surrounding gate MOSFETs are compared fr...
Abstract — This paper reports recent progress on partially depleted (PD) SOI modeling using a surfac...
The accuracy of the existing metal-oxide-semiconductor-field-effect-transistor (MOSFET) models used ...
Abstract—This work describes an advanced physics-based com-pact MOSFET model (SP). Both the quasista...
In this paper, a small-signal MOSFET model is described, which takes the local effects of both veloc...
This paper reviews present compact model development and outlines the main features of the PUNISM, a...
Like other surface-potential based model, our surface-potential-plus model starts with charge-sheet ...
In this paper the capacitance components of the PSP compact model which is selected as successor of ...
This paper presents a new and more accurate potential based model for bulk MOSFET compared to the tr...
Abstract. This paper addresses current issues in compact MOSFET modeling, provides an overview and s...
This paper reviews present compact model development and outlines the main features of the PUNISM, a...
This paper outlines the charge-based core and the model architecture of the BSIM5, an advanced charg...
With the continuous scaling of CMOS technologies, Silicon-on-Insulator (SOI) technologies have becom...