TESTING AND VERIFICATION OF (7, 4) HAMMING CODE USING HDL

A communication system mainly comprises of a transmitter section and a receiver section linked through a channel. Such a system is said to be efficient if the data received at the receiver is exactly what was transmitted. But it is a well known fact that, the message transmitted can get distorted due to several disturbances in its path. In order to reduce the occurrence of error in digital communication system, the message signal will be coded using an encoder. At the receiver section, a decoder is used for the purpose of decoding the signal. This project is intended to analyze the encoder and decoder using Hamming code. Hamming code is a linear block code. In the encoder, parity symbols are generated using generator polynomial. Hamming code is capable of correcting all error patterns with a single error or detecting all the error patterns of two or fewer errors. The project proposes encoding algorithm, synthesis and simulation using Verilog HDL. The implementation of Hamming code encoder using Spartan-6 FPGA kit was also done. KEYWORDS: HDL, LB