Reconfigurable Pipeline Skeleton for Parallel Applications Codesign on High-Performance Heterogeneous Computing Systems

Reconfigurable heterogeneous computing systems (RHCS) have been used to exploit parallelism by means of coupled and coordinated processing between FPGA and different computing devices. However, these systems have high programming complexity due to the details associated with parallelism and FPGA logic design. Therefore, the development of the hardware and software components of an application at the same level of abstraction has been difficult to achieve. Several techniques have been described in the literature that attempt to reduce such complexity to the programmer, but without achieving sufficient transparency and abstraction. In this paper we introduce a reconfigurable pattern of parallel ‘pipeline’ computing, called PipeSkeleton. It is an algorithmic skeleton provided as a high-level template in openCL code. This tool uses Cole’s Algorithmic Skeletons to transparently exploit parallelism by hiding the details of its implementation and FPGA reconfiguration. Thus, the programmer can write high-performance parallel applications independent of the available heterogeneous computing system architecture. As a demonstration, a tests suite with different configurations integrating hardware and software components are described. For each configuration, measures of the cost in execution time and amount of resources used were taken. It was shown that configurations with hardware-implemented kernels and software-implemented data input/output run faster and consume fewer resources. As conclusion, the tool provides to the programmer the abstraction level to easily move functionalities between software and hardware during the exploration stage of application design spaces