Design of passive heat sinks to power semiconductor with the Cesaro curve

In the design of electronic circuits, stands out the power stage, which is responsible of increasing the signal characteristics, as current and voltage, for an appropriate performance of the device to fabricate. However, this stage is composed of elements like transistors, which may have a low performance, due to the undesired temperature increase, as a result of reaching the desired power. To mitigate the loss of power and with it, the temperature rise, the management of heat sink is proposed, in order to keep the work of the power stage at a stable level and avoid thermal fractures within the circuit. This manuscript presents the obtained results of the thermal analysis in finite elements of the heat sink with fins in the form of a Cesaro curve, for power semiconductors, which evidence the increase in the heat flow, with respect to the commercial ones and so, facilitate the heat evacuation for conditioning the voltage and/or current