Enabling Standalone FPGA Computing

One of the key obstacles in the advancement of large-scale distributed FPGA platforms is the ability of the accelerator to act autonomously from the CPU, whilst maintaining tight coupling to system memory. This work details out efforts in decoupling the networking capabilities of the FPGA from CPU resources using a custom transport layer and network protocol. We highlight the reasons that previous solutions are insufficient for the requirements of HPC, and we show the performance benefits of offloading out transport into the FPGA fabric. our results show promising throughput and latency benefits and show competitive Flops being achievable for network dependent computing in a distributed environment