ANALYSIS OF 6T SRAM CELL USING FINFET AT NANOMETER REGIME

The fast growing technology developments in the met al oxide semiconductor area have scaled down CMOS t o the sub 32nm regime. According to International Technol ogy Roadmap For Semiconductors projection by the 20 20,the printed gate lengths will scale down to 12nm. Inste ad of SiO2 with AL metal gate Hafnium Oxide [HFO2] can be used as a High k material. To increased chip functi onality demand,SRAM area have mostly exceed overal l chip area. The stability of SRAM cell depends on variati on in Process,Temperature and Voltage. This paper will discuss the detail about 6T SRAM stability in standby,read and write mode design considering Double Gate MOSF ET at 32nm technology node. https://www.ijiert.org/paper-details?paper_id=14042